Arteris IP

  • Arteris IP Welcomes Back Veteran Laurent Moll as Chief Operating Officer

  • Arteris® IP Adds a Record 28 New Licensees in 2020

  • Arteris® IP Adds Two Veteran Executives to its Board of Directors

  • Arteris® IP FlexNoC® Interconnect and Resilience Package Supports Socionext's 5nm Automotive Chip Production

  • Arteris® IP FlexNoC® Interconnect and Resilience Package Licensed by Hailo for Artificial Intelligence (AI) Chip

Omni-Des

  • September 7, 2021
    Omni Design and LeddarTech Collaborate to Accelerate Mass Market Deployment of LiDAR for ADAS and Autonomous Vehicles

  • September 7, 2021
    Omni Design Opens Design Center in Fort Collins, Colorado

  • August 3, 2021
    Omni Design Announces Silicon Validated Gigasample+ Low Power ADC and DAC on TSMC 28nm Technology

  • June 23, 2021
    GUC and Omni Design Tape Out 16nm LiDAR SoC

  • June 23, 2021
    AST & Science Selects Omni Design to Provide High Performance Data Converter Solutions for its Cellular Broadband Network

Codasip

  • Codasip Announces Fpga Evaluation Platforms For Risc-V Processor Cores

  • Codasip Releases A Major Upgrade Of Its Studio Processor Design Toolset With A Tutorial Risc-V Core

  • Codasip To Offer Secure Boot Solutions With Veridify Tools

  • Valtrix And Codasip Cooperate On Verification Of Risc-V Systems

  • Ron Black Joins Codasip As Executive Chairman

  • Codasip Announces Commercial Add-Ons To Swerv Core® Eh1

  • Tianyihexin Licenses Codasip L30 For Powering Intelligent Wearable Device Solutions

  • Menta Efpga And Codasip Announce Technology Partnership

  • Codasip Announces Three New Risc-V Application Processor Cores Providing Multi-Core And Simd Capability

  • Neulinker Licenses Codasip Bk5 And Studio For Powering Innovative Ai And Blockchain Solutions

Movellus

  • Esperanto Technologies Adopts Movellus Maestro AI, Intelligent Clock Networks for Its ET-SoC-1 Chip

  • Movellus Launches Maestro Intelligent Clock Network Platform for SoC Designs

  • Achronix Adopts Movellus Maestro Clock Network for Its Speedster7t FPGAs

  • Syntiant Adopts Movellus’ Clock Network for its Low-Power NDP120 Deep Learning Processor

  • Movellus CEO Mo Faisal to Present at Linley Spring Processor Conference