Interconnect IP

'S NoC (Network-on-Chip) solution brings the concepts of networks into the System-on-a-Chip enabling the interconnect to be smaller, lower power dissipation, and operate at higher frequencies. It consists of the Danube Intellectual Property Library and a suite of design tools for configuring and implementing the IP library as synthesizable RTL. The Danube Intellectual Property Library contains a set of configurable building blocks managing all on-chip communications between IP cores in SoC designs.

NoC’s key features are:

• Can connect to processors, DSPs, HW accelerators, I/O peripherals, memories, etc., regardless of the socket interfaces the blocks use to communicate: AHB, AXI, OCP, or other proprietary interfaces
  
• Can be structured as a hierarchy of sub-networks, or "clusters", allowing fully independent SoC subsystem design, or reuse of existing subsystems
  
• Easy exploration of various architectures for a given traffic
  
• Easy analysis of different architectures under different traffics constraints
  
• NoCverifier, the integrated VMM-based NoC verification tool